The present invention relates to a method and/or architecture of a programmable logic device generally and, more particularly, to real time programmable control of features in a programmable logic device (PLD).
A programmable logic device (PLD) allows programmable logic to be implemented in an integrated circuit. Conventional PLDs have configuration bits that select low power, slew rate, and I/O drive standards. The configuration bits are programmed when a design is created. The configuration bits (and thus the features controlled by the configuration bits) cannot be changed while the device is operating (i.e., in real time). If the feature selections need to be changed, the conventional programmable logic device must be reprogrammed.
The use of configuration bits requires that feature settings be determined at the time the PLD design is compiled and programmed. Because the configuration bits are fixed, the design of a PLD can require compromises. For example, a low-power feature may be desirable for a majority of the time a PLD is operating. However, if one particular set of operations requires a faster high-power mode, the conventional PLD design will be unable to take advantage of the low-power feature.
Inherently low power PLDs such as the xe2x80x9cCool-Runnerxe2x80x9d family from Xilinx (formally from Philips) use a full CMOS implementation for the product term array eliminating the need for sense-amps that burn DC power. The inherently low power devices can use more die area than similar sense-amp based devices. Although the inherently low power devices can provide a solution for achieving the lowest power budget using a CPLD, the advantage is limited purely to power and can incur a die size/cost penalty depending on the technology used.
Some operations of the conventional PLDs are real time programmable. PLD vendors offer dedicated product terms for real time control of logical operations of macrocells and I/O buffers. For example, conventional PLDs offer reset (RPT), preset (SPT) and clock product terms (PTCLK) that can control a macrocell logic operation in real time. PLDs also provide dedicated OE product terms to control a tri-state level of output buffers in real time. However, real time control capability of other non-logic features is not available. For example, Lattice PLDs allow programming analog characteristics, but not in real time. SRAM based PLDs require setting configuration bits at the time of programming. Despite the lack of real time programmability, non-logic features are becoming more common in PLD devices.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first plurality of signals in response to one or more input signals. The second circuit may be configured to generate one or more control signals in response to said first plurality of signals. The one or more control signals may control one or more non-logic features.
The objects, features and advantages of the present invention include providing a method and/or architecture for real time programmable control of non-logic features in a programmable logic device that may: (i) dynamically change a configuration of any feature implemented on the device, (ii) control a low or zero power mode on sense-amp based programmable logic devices, (iii) dynamically control non-logic features of the device, (iv) control non-logic features of the device using dedicated product terms, (v) control power consumption of logic blocks independently, (vi) control features such as I/O slew rate and drive characteristics in real time, and/or (vii) allow logic implemented in one logic block to control features in other logic blocks.